The invention relates to a semiconductor device having a charge-coupled memory device of the SPS type formed at a surface of a semiconductor body and including
a series input register comprising a series of charge storage sites, in which data can be stored in the form of charge packets, PA1 a parallel section coupled to the series input register and comprising a number of adjacent parallel registers, which each correspond to one of the storage sites of the series input register, PA1 a system of clock electrodes, which are connected via clock lines to clock voltage sources for applying clock voltages having a first level at which the semiconductor body has induced in it a potential well, in which charge can be stored, and a second level through which charge is pushed to an adjacent storage site PA1 an input stage in series with the series input register comprising an input diode and a sampling electrode, which is located between the diode and the first storage site of the series input register and is connected via one of the clock lines to other clock electrodes of the series input register and by means of which in the semiconductor body a potential well can be induced, in which by means of the input diode charge packets can be formed, which are representative of the data supplied PA1 signal supply means for supplying data which are converted into charge packets by the input stage. Devices of this type are known, for example, from Chapter 4 "Application of CCD's to Memories" by Kosonocky and Zaininger, published in the book "Charge-Coupled Devices and Systems", edited by Howes and Morgan (John Wiley and Sons, New York 1980). A possible application of CCD memories is described inter alia in the article "A digital field memory for television receivers" by Pelgrom et al, published in I.E.E.E. Transactions on Consumer Electronics, Vol. CE-29, No. 3, August 1983, pp. 242/248. This article discloses a memory, in which video signals of one T.V. picture, after having been 8-bit encoded, are read in serially into the input register and are read out again serially at the output of the output register.
It is already indicated in the aforementioned book of Howes and Morgan that clock voltages can be used at which the voltage at an electrode under which charge has been stored is reduced, as a result of which the potential well under this electrode becomes less deep and the charge is transported to an adjacent storage site. Because of the pushing effect occurring during this charge transport, this mode of operation is often designated as "push clocking". Besides this method, also the so-called "drop clocking" method is known, in which charge stored under a first electrode is transported by increasing the voltage at an adjacent electrode, as a result of which a deeper potential well is formed under the adjacent electrode.
Due to the fact that the storage capacity is not determined, as in the "drop clocking" method, by inner potential barriers, the charge storage capacity in the "push clocking" method can be higher. The signal to be read in can be supplied to the input diode or to a separate signal electrode located between the sampling electrode and the input diode. During reading-in, a charge packet is formed under the sampling electrode, which packet is a measure for the data read in. With binary data, this charge can be a quantity q for a "1" and a zero charge for the signal "0". After reading-in, this charge can be transported through the input register by means of the "push clocking" method described above and, when the input register is full, it can be transferred to the parallel section.
It has been found that, when reading out supplied data in the "push clocking" method described here, distortion of the signals often occurs. Further examinations have shown that this distortion is strongest with data transported via parallel registers located closest to the input.